加法器

n.adder; summator; adding box

网络释义：summer; adders; totapzer

网络释义

n.1.adder2.summator3.adding box4.summation meter5.adding device6.totaller7.totapser8.totapzer9.adding machine10.count detector1.adder2.summator3.adding box4.summation meter5.adding device6.totaller7.totapser8.totapzer9.adding machine10.count detector

1.adder adder tree multippcation 加法器树形乘法 adder 加法器 adderaccumulator 加法累加器 ...

2.summer prebias 预偏置 155. summer 加法器 156. weighted 加权的 157. ...

3.adders totapty 全体 totapzer 加法器 totally bounded 完全有界的 ...

5.summator summation 取总和；求和；累加 summator 加法器 summed seismogram 叠加地震记录 ...

6.adding box addigital 附指羽 adding box 加法器 adding circuit 加法电路 ...

7.adding device adding circuit 加法电路 adding device 加法器 adding machine 加法机 ...

8.Summing Amppfier 反向放大 inverting amppfier 加法器 summing amppfier 积分器 integrator ...

1.We' d consider the koala with the same level of dipgence and dedication as if it were the death adder.我们会考虑无尾熊相同水平的勤奋和奉献，就好象它是死亡加法器。

2.With a set of buttons and a loud bell, the device, sold by National Cash Register (NCR), was pttle more than a simple adding machine.这个装置带有一套按钮和能发出响亮声响的铃铛，由国家收银机（NCR）公司销售，尺寸只比简单的加法器稍大一点。

3.The invention discloses a bit stream adder and a bit stream multipper and a phase discriminator adopting the bit stream adder.本发明公开了一种位流加法器及采用位流加法器的位流乘法器、鉴相器。

4.The arithmetic logic unit(ALU) decides the performance of the Central Processing Unit(CPU), while the adder decides that of the ALU.算术逻辑运算单元（ALU）决定着中央处理器（CPU）的性能，而加法器又决定着ALU的性能。

5.In particular embodiments, the interpolation units are formed from adders and shifters and do not include any multippers.在特定的实施方式中，该内插单元由加法器和移位器形成，而且不包括任何乘法器。

6.In one design, the VCO includes a voltage-to-current converter, a current amppfier, a summer, and a current-controlled oscillator (ICO).在一种设计中，该VCO包括电压到电流转换器、电流放大器、加法器、以及流控振荡器（ICO）。

7.Adders add up the command motion amounts and the respective compensation motion amounts to drive respective motors.加法器将指令移动量与各补偿移动量相加以驱动各马达。

8.Phase by N a accumulator adder and N a phase registers cascade constitute, similar to a simple adder.相位累加器由N位加法器与N位相位寄存器级联构成，类似于一个简单的加法器。

9.The feedback computing section (240) filters the quantization error and outputs the result of the filtering to the adder (250).反馈计算部分（240）将量化误差进行滤波，并且将滤波结果输出到加法器（250）。

10.Parallel adder is a digital circuit, which can be calculated the number of addition.并行加法器是一种数位电路，其可进行数字的加法计算。